Performance characteristics of cascaded delay‐line node architectures in single‐path interconnection networks

Internally buffered multistage interconnection network architectures have been widely used in parallel computer systems and large switching fabrics. Migration from electrical domain to optical domain has raised the necessity of developing node architectures with optical buffers. Cascaded fibre delay line architectures can be seen as possible realizations of output and shared buffering in a 2 × 2‐switching element. These approaches can be used as buffered node architecture in a Banyan like interconnect. In this paper, we investigate and compare these approaches by using simulation methods. Different performance metrics, such as normalized throughput, average packet delay, packet loss rate and buffer utilization have been used under uniform and non‐uniform traffic models. Results show that the TC‐chain node Banyan network offer an improved normalized throughput and average packet delay performances under both traffic models without disrupting first‐in‐first‐out order of arrivals. The switched delay‐line requires fewer switching elements than TC and TTC architectures but at the cost of high packet delay. Copyright © 2004 John Wiley & Sons, Ltd.     

城市规划中的水资源承载力计算——以惠州市为例

探讨水资源承载力综合评估和多目标计算理论在城市规划中的应用。运用灰色多层次综合评估模型对惠州市水资源承载力进行定性的综合评价,应用多目标规划理论对城市经济发展规划不同方案下的惠州市水资源承载力作了定量计算。     

An analog circuit design environment based on cooperating blackboard systems

A novel approach to design automation for analog circuits is presented. The prototype implementation-OASE-has been realized as a set of cooperating expert systems with blackboard architecture. The circuit specific knowledge bases use hybrid representation schemes and are strictly separated from an execution engine containing the necessary control knowledge. This alleviates the knowledge acquisition process as well as the extension and maintenance of existing knowledge. OASE has been developed as a design assistant, featuring different levels of interactivity, a hierarchical design style and fully embedded algorithmic standard tools. In its current version it is able to design a broad range of different CMOS operational amplifiers.     

A review on queueing network models with finite capacity queues for software architectures performance prediction

A review is carried out on how queueing network models with blocking have been applied so far into the performance evaluation and prediction of Software Architectures (SA). Queueing network models with finite capacity queues and blocking have recently been introduced and applied as more realistic models of systems with finite capacity resources and population constraints. Queueing network models have been often adopted as models for the evaluation of software performance. Starting from our own experience, we observe the need of a more accurate definition of the performance models of SA to capture some features of the communication systems. We consider queueing networks with finite capacity and blocking after service (BAS) to represent some synchronization constraints that cannot be easily modeled with queueing network models with infinite capacity queues. We investigate the use of queueing networks with blocking as performance models of SA with concurrent components and synchronous communication. Queueing theoretic analysis is used to solve the queueing network model and study the synchronous communication and performance of concurrent software components. Our experience is supported by other approaches that also propose the use of queueing networks with blocking. Directions for future research work in the field are included.     

Keynote paper: Architectures for integrating manufacturing activities and enterprises

This paper is a summary of the major technical report (Williams et al., 1993) of the IFAC/IFIP Task Force on Architectures for Integrating Manufacturing Activities and Enterprises. It presents a synopsis of the investigations of pertinent architectures undertaken, and the findings generated relating to the suitability of various architectures for the integration task. It also presents the Task Force's recommendations for achieving a “complete” architecture in terms of the necessary capabilities by “completing” a currently available architecture. The Task Force also outlined how a “best” architecture could be achieved by selecting and combining the best features of the available architectures.     

珠江口盆地惠州地区中新统地层岩性圈闭形成条件分析

区域地质背景反映珠江口盆地惠州地区中新统具有形成地层岩性圈闭的条件。研究惠州地区地层岩性圈闭的形成条件、控制因素和分布规律,对于该区油气勘探持续发展有重要意义。建立了惠州地区中新统高精度的层序地层格架,在此基础上分析不同类型层序的构型特点,研究不同类型坡折带的形成机制、分布范围及对沉积体系的控制作用。层序地层边界和坡折带是控制本区地层岩性圈闭形成的重要因素。惠州地区存在3种具有勘探前景的地层岩性圈闭,选择HZ27-3低位体钻探获得成功。     

Parallelization of WHILE loops on pipelined architectures

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. This paper shows that a broader class of loops—REPEAT-UNTIL, WHILE, and loops with more than one exit, in which the trip count is not known beforehand—can also be overlapped efficiently on multiple-issue pipelined machines. The approach is described with respect to a specific machine model, but it can be extended to other models. Special features in the architecture, as well as compiler representations for accelerating these loop constructs, are discussed. Performance results are presented for a few select examples.An earlier version of this paper was presented at Supercomputing '90.     

海陆交互相三角洲高分辨率层序地层探析——以珠江口盆地惠州凹陷珠海组为例

针对海陆交互地区三角洲沉积体系特征，采用高分辨率层序地层多级次基准面旋回划分方案，通过对地震与测井等资料的综合分析，研究珠江口盆地惠州凹陷珠海组海陆交互相三角洲沉积体系的高分辨率层序地层学特征，在珠海组中识别出短期、中期和长期3个级别的基准面旋回。在此基础上，运用等时对比法则对各级旋回进行对比并建立层序地层格架，归纳了珠海组沉积时期2个长期基准面旋回内的沉积体系演化规律及其特征。     

PERFORMANCE ANALYSIS OF TASK CLUSTERING HEURISTICS FOR SCHEDULING STATIC DAGS ON MULTIPROCESSOR SYSTEM*

CASS is a task management system that provides facilities for automatic grain-size optimization and task scheduling of parallel programs on distributed memory parallel architectures. The heart of CASS is a clustering module that partitions the tasks of a program into clusters that match the granularity of the target machine. This paper describes the clustering algorithms used by CASS and compares them with the best known algorithms reported in the literature, namely the PY algorithm (for clustering with task duplication) and the DSC algorithm (for clustering with no task duplication). It is shown that the clustering algorithms used by CASS outperform both the PY and DSC algorithms in terms of both speed and solution quality.